The past few years have seen a dramatic increase in the speed of data transmission between various components of a computer system or between multiple computer systems connected together in a network. Indeed, since general acceptance of personal computer systems in the 1960's, data transmission speeds have grown with an almost power law dependence; about 1 MHz in the '60's, 10 MHz in the '70's, 100 MHz in the '80's, and 1 GHz speeds being routinely achieved in the '90's.
Optical fibre is a particular enabling technology for modern day 1 GHz data transmission speeds and, in the computer industry, has given rise to a data transfer protocol and interface system termed Fibre-Channel. Fibre-Channel technology involves coupling various computer systems together with optical fibre or a fibre channel-type electrically conductive (copper) cable and allows extremely rapid data transmission speeds between machines separated by relatively great distances. However, because of the physical characteristics of fibre channel-type cable, present day systems are only capable of serial-fashion data transmission (at least when only a single optical fibre or electrical cable is used to interconnect various computer systems). However, computer systems are constructed to almost universally handle data in parallel fashion on byte-multiple signal busses (8-bit, 16-bit or 32-bit busses), making it incumbent on any data transmission system to provide some means for converting a 1 GHz serial data stream into a byte or byte-multiple parallel data stream. Conversely, since the fibre channel protocol is 2-way, computer systems that typically operate with parallel data structures, must have some means for serializing a byte or byte-multiple data stream into a 1 GHz data signal suitable for transmission down an optical fibre or electrically conductive (copper) cable.
Parallel data being serialized for high speed transmission, is typically synchronous, in that the sequence of 1's and 0's making up the resulting serial data stream occurs with reference to a uniform or single-frequency serializer clock signal. Encoding and transmitting the clock signal, together with the data, would take up inordinate amounts of valuable signal bandwidth and reduce the overall data transmission speed of a fibre channel system. Even though some small degree of self-clocking is inherent in the serial data stream, some method of evaluating the data stream must be used in order that a transceiver or serial-to-parallel data recovery system may determine how to appropriately frame the binary data stream into bytes.
In many applications, this function is performed by various types of data synchronizers, which generate or regenerate a synchronous timing reference signal from a serial data stream and provides the timing reference to a serial-to-parallel converter, such as a sequential latch. In effect, a data synchronizer generates a synchronous stream of successive timing references, each timing reference representing a bit cell with which a data bit is associated. For example, 10 consecutive timing references might represent an 8-bit data word followed by 2 bits of error correction code which might then be latched out onto a 10-bit parallel data bus by a, for example, 10-bit counter. The data synchronizer, accordingly, is an essential component in modern day gigahertz serial to parallel data converters.
However, the frequency of clock signals synthesized by such circuitry is subject to a number of variations introduced by the electronic components of such systems. Typically, the electronic components in the data path introduce elements of phase and frequency noise which are random in nature and, more particularly, have dramatically varying bandwidth characteristics depending on the geometric and electronic variations in modern semiconductor manufacturing process parameters. A synchronizer, such as a 1.06 GHz to 106 MHz Transceiver, must take these variations into account when attempting to deal with a 1.06 GHz serial data stream. Implementations of such a synchronizer or transceiver, typically include at least phase-locked loop (PLL), normally comprising a phase or phase and frequency detector, a charge pump, an analog filter, and means for generating a synchronous clock signal, such as a voltage controlled oscillator (VCO). When receiving data, during what is conventionally termed frequency or velocity lock, the oscillation frequency of the VCO is determined by, and locked to the frequency of an external clock provided for such purpose, just prior to receiving the serial data stream. Once frequency or velocity lock is established, the VCO runs in what might be termed a quasi-flywheel mode at a mean frequency determined during velocity lock. Subsequent correction control to the VCO frequency is developed by phase-locking a transition edge of the synchronous VCO signal to a transition edge of an incoming data signal. The VCO is phase-locked to the incoming serial data stream by comparing, the phase of the rising edge of the VCO clock signal to the phase of the rising edge of a data One (1) bit, in a phase detector. A phase or time difference detected between the two rising edges causes a charge pump to generate a control voltage, directing the VCO to either speed up or slow down in response to frequency variation in the data stream.
An analog low pass filter is typically provided between the charge pump and the VCO to reject corrections resulting from random high-frequency variations of individual data bits, and allow ideally only corrections resulting from consistent frequency shifts of the data stream. The VCO is therefore locked to the mean phase of the data stream, rather than to the phase of a particular data bit. Once phase-locked, the synchronous VCO signal provides for a recovered clock signal whose rate (frequency) is equal to the data bit rate or an integral multiple thereof.
The typical prior art phase-locked loop system is illustrated in FIG. 1, and is connected to receive an incoming serial data stream from, for example, an optical fibre cable 10. The phase-locked loop suitably comprises a phase detector 11, coupled to a charge pump 12, an analog filter 13, and a voltage controlled oscillator or VCO 14.
Serial data is directed over the, for example, optical cable 10 to an input of the phase detector 11, in which its phase is compared to the phase of the output signal of the VCO 14. The output of the phase detector 11 comprises 2 signals, pump-up (or UP) 16 and pump-down (or DN) 18 which, in turn, direct the charge pump 12 to apply a source or sync current to the analog filter 13 which develops a voltage control signal for the VCO 14. Conventionally, the pulse detector 11 issues UP 16 if the data stream leads the VCO signal, and issues DN 18 if the serial data stream phase lags the signal stream from the VCO 14. UP 16 and DN 18 are directed to the charge pump 12 which sources or sinks a particular amount of current (denoted herein I.sub.CP) to or from, respectively, the filter 13. The filter 13 includes at least a resistor across which a voltage is developed as the charge pump current I.sub.CP is sourced or sunk to or from a capacitor in well known fashion, causing controlled changes to the VCO control voltage (V.sub.C). The sign of the VCO control voltage variation depends on whether the phase of the data stream leads or lags the phase of the VCO output, and its magnitude is a function of the extent of the lead or lag. Thus, the output frequency of the VCO 14 is increased or decreased, as appropriate, to reduce the lead or lag at the inputs to the phase detector 11. The phase-locked loop thus ensures that the VCO output, which may be used as a timing reference, is locked in phase with the incoming serial data stream.
The primary shortcoming of prior art phase-locked loop systems is that their response times and stability characteristics depend on bandwidth. For example, PLL bandwidth is directly proportional to time-to-lock, i.e., the time it takes for a PLL to establish a stable frequency or velocity lock to an external clock. In addition, PLL bandwidth has a direct effect on the stability of a PLL system. A VCO output signal is generally regular and periodic, whereas the occurrence of a data bit in a serial data stream is irregular. With inadequate bandwidth, this may lead to a run away correction condition, as the charge pump constantly attempts to correct for irregular phase lags or phase leads.
PLL bandwidth is generally recognized as being a function of the charge pump current (I.sub.CP) the analog filters' resistor (denoted herein as R.sub.1) and the gain of the VCO (denoted as K.sub.VCO), and is given by the expression:
.OMEGA..sub.0 =R.sub.1 I.sub.CP K.sub.VCO
Power supply voltage fluctuations, circuit temperature variations and manufacturing process parameter drift all combine to vary the filter resistance, charge pump current and VCO gain, thus distorting the PLL's bandwidth characteristic, making it less-than-ideal. This bandwidth distortion has significant implications for high-speed, low error rate, fibre channel data transmission systems.
Certain attempts have been made in recent years to design PLL's for bandwidth stability using the specified centers of a specific set of manufacturing process parameters. Such designs function adequately if the manufacturing process parameter tolerance range does not vary more than approximately 1 sigma (.sigma.) from the parameter centers. If, however, the process tolerances are within specification, but at the tolerance corners, PLL bandwidth is often seen to vary according to a 1 to 8 ratio (approximately 0.5 to approximately 4.0 MHz). The time-to-lock is decreased in a manner directly proportional to the decrease in bandwidth as is the degree of over damping or under damping and stability.
Accordingly, there is a demonstrated need for a phase lock loop system in which bandwidth is maintained at a relatively constant value regardless of power supply voltage fluctuations, temperature variations and manufacturing process parameter drift. Such a PLL will be able to demonstrate a generally constant bandwidth characteristic during changing environmental conditions such as during circuit initialization operations, and initial velocity lock after a significant period of down-time.